Protel Design System Design Rule Check
PCB File : C:\Users\Di\Dropbox\collaborations\DiTsi\0_projects\UstanovkaDlyaZasvetki\uC_PCB\PCB1.PcbDoc
Date     : 16/04/02
Time     : 20:51:12

WARNING: Zero hole size multi-layer pad(s) detected
   Pad J1-2(10.719mm,55.035mm) on Multi-Layer on Net GND
   Pad J1-3(5.719mm,52.035mm) on Multi-Layer on Net NetJ1_3
   Pad J1-1(10.719mm,48.835mm) on Multi-Layer on Net +24V

WARNING: Multilayer Pads with 0 size Hole found
   Pad J1-2(10.719mm,55.035mm) on Multi-Layer
   Pad J1-3(5.719mm,52.035mm) on Multi-Layer
   Pad J1-1(10.719mm,48.835mm) on Multi-Layer

Processing Rule : Clearance Constraint (Gap=0.254mm) (InComponent('U1')),(IsRegion)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
   Violation between Short-Circuit Constraint: Between Track (35.604mm,44.704mm)(35.814mm,44.704mm) on Bottom Layer And Pad U1-15(35.814mm,44.704mm) on Multi-Layer Location : [X = 66.316mm][Y = 77.724mm]
Rule Violations :1

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
   Violation between Clearance Constraint: (0.225mm < 0.254mm) Between Track (37.7mm,22.1mm)(37.7mm,26.9mm) on Top Layer And Via (39.2mm,22.9mm) from Top Layer to Bottom Layer 
Rule Violations :1

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=0.3mm) (Max=5mm) (Preferred=0.35mm) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
Rule Violations :0

Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (Disabled)(All),(All)
Rule Violations :0

Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0

Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=0.178mm) (InComponent('U1')),(OnLayer('Top Layer'))
Rule Violations :0


Violations Detected : 2
Time Elapsed        : 00:00:00